M128-010 M128-010-A001B

Brand: MOOG

Type:M128-010 M128-010-A001B

Origin: the United States

Warranty: 365 days

Colour: new/used

Shipping method: Courier delivery

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Memory Maps There are two points of view for memory maps: ❏ The mapping of all resources as viewed by local bus masters (local bus memory map) ❏ The mapping of onboard resources as viewed by VMEbus masters (VMEbus memory map) Local Bus Memory Map The local bus memory map is split into different address spaces by the Transfer Type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes. Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the TT signals on the local bus. For the MVME162, transfer types 0, 1, and 2 define the normal address range. Table 3-1 defines the entire map ($00000000 to $FFFFFFFF). Many areas of the map are user-programmable, and suggested uses are shown in the table. The cache inhibit function is programmable in the MC68xx040 MMU. The onboard I/O space must be marked ‘‘cache inhibit’’ and serialized in its page table. Table 3-2 further defines the map for the local I/O devices.

1. Reset enables the decoder for this space of the memory map so that it will decode address spaces $FF800000 - $FF9FFFFF and $00000000 - $003FFFFF. The decode at 0 must be disabled in the MCchip before DRAM is enabled. DRAM is enabled with the DRAM Control Register at address $FFF42048, bit 24. PROM/Flash is disabled at the low address space with PROM Control Register at address $FFF42040, bit 20. 2. This area is user-programmable. The DRAM and SRAM decoder is programmed in the MCchip, the local-to-VMEbus decoders are programmed in the VMEchip2, and the IP memory space is programmed in the IPIC. 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped.