IC698CMX016-ED VMIVME-5567-000 350-005567-000 E

Brand: GE

Type:IC698CMX016-ED VMIVME-5567-000 350-005567-000 E

Origin: the United States

Warranty: 365 days

Colour: new/used

Shipping method: Courier delivery

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Onboard DRAM The MVME162 offers a 1MB, a 4MB, and an 8MB DRAM option. The DRAM architecture is non-interleaved for 1MB and interleaved for 4MB and 8MB. Parity protection can be enabled with interrupts or bus exception when a parity error is detected. DRAM performance is specified in the section on the DRAM Memory Controller in the MCchip Programming Model in the MVME162 Embedded Controller Programmer’s Reference Guide. The DRAM map decoder can be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed. Refer to the MCchip description in the MVME162 Embedded Controller Programmer’s Reference Guide for detailed programming information. Most DRAM devices require some number of access cycles before the DRAMs are fully operational. Normally this requirement is met by the onboard refresh circuitry and normal DRAM initialization. However, software should insure that a minimum of 10 initialization cycles are performed to each bank of RAM.

Battery Backed Up RAM and Clock An MK48T08 RAM and clock chip is used on the MVME162. This chip provides a time-of-day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are automatically made. No interrupts are generated by the clock. Although the MK48T08 is an 8- bit device, the interface furnished by the MCchip supports 8-, 16-, and 32-bit accesses to the MK48T08. Refer to the MCchip description in Chapter 3 and to the MK48T08 data sheet for detailed programming and battery life information. VMEbus Interface and VMEchip2 The optional VMEchip2 provides the local-bus-to-VMEbus and VMEbus-tolocal-bus interfaces. The VMEchip2 can also provide the VMEbus system controller functions. Refer to the MVME162 Embedded Controller Programmer’s Reference Guide for detailed programming information. Refer to the MVME162 Embedded Controller Support Information manual for the pin assignments of VMEbus backplane connectors P1 and P2. Note that the ABORT switch logic in the VMEchip2 is not used. The GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not used. The ABORT switch interrupt is integrated into the MCchip ASIC at location $FFF42043. The GPI inputs are integrated into the MCchip ASIC at location $FFF4202C, bits 23-16.