ADI AD9273BBCZ-40 DC-DC Power Supply Chip Bidirectional, Zero Drift, Current Sense Amplifier

feature

Single 3 V supply operation (2.7 V to 3.6 V)

SNR = 70 DBC to Nyquist, with 65 MSP

SFDR = 85 DBC to NYQUIST, 65 MSPS to Nyquist

Low Power: 300 MW of 65 MSP

Differential input for 500 MHz bandwidth

On-chip reference and SHA

DNL = ±0.4 LSB

Flexible analog input: 1 V P-P to 2 V P-P range

Foreclose binary or two supplementary data formats

Clock duty cycle stabilizer

Apply

Ultrasonic equipment

If sampling is performed in a communication receiver

IS-95, CDMA-ONE, IMT-2000

Battery-powered instruments

Handheld scopemeters

Low-cost digital oscilloscope

Functional block diagram

Sha

Vin+

vin -

drvdd

Stage 8

1 1/2 bits

pipeline

CLK PDWN mode

bell

Duty Cycle

Stabilizer

model

choose

DGND

OTR

D11

D0

avdd

MDAC1

Correction logic

Output buffer

refer to

choose

agnd

0.5V

vref

Feel

AD9235

Reft

refb

advertise

advertise

4 16

12

3

Figure 1.

General description

AD9235 is a single chip, single 3 V supply family, 12-bit,

20/40/65 MSP analog to composition converter (ADC). this 

Home with high performance samples and held amplifiers

(SHA) and voltage reference. AD9235 multi-stage use

Differential pipeline architecture with output error correction

Logic provides 12-bit accuracy at 20/40/65 MSPS data rate

And ensure that code is not lost throughout the operation

Temperature range.

Wide bandwidth, true difference sha allows for multiple

User-selectable input ranges and offsets include single-ended

Apply. It is suitable for switching multiplexing systems

Full-scale voltage levels for continuous channels and sampling

The frequency of a single-channel input is far beyond the Nyquist rate. 

Combined with previously available power and cost savings

ADC, AD9235 is suitable for communication, imaging and medical ultrasound applications.

Single-ended clock input is used to control all internals

Conversion cycle. Duty Cycle Stabilizer (DCS) Compensation

While maintaining widespread changes in clock duty cycle

Excellent overall ADC performance. The digital output data is

Presented in straight binary or two complement format. one 

Range (OTR) signal indicates overflow condition

Can be used with the most important bits to determine the low or

High overflow.

The AD9235 is manufactured in the Advanced CMOS process and can be used in 28 lead TSSOP and 32 lead LFCSP and specified

In industrial temperature range (–40°C to +85°C).

Product Highlights

1. The AD9235 is run by a single 3 V power supply,

A separate digital output driver supply is provided for Accommo dated 2.5 V and 3.3 V logic series.

2. Operating at 65 MSP, the AD9235 consumes 300 MW lower.

3. Patented SHA input maintains excellent performance

Input frequency up to 100 MHz, can be configured

Single-ended or differential operation.

4. AD9235PINOUT is similar to AD9214-65, 10 bits,

65 MSP ADC. This allows from

10-12 bits for 65 MSP systems.

5. Clock DCS maintains overall ADC performance on A

Wide range of clock pulse widths.

6. OTR output bit indicates when the signal exceeds

Selected input range.