AWR2944ABGALTRQ1

FMCW transceiver

Integrate PLL, transmitter, receiver, baseband, and ADC

Coverage range from 76GHz to 81GHz, with available bandwidth of 5GHz

4 receiving channels and 3 to 4 sending channels (3 channels for AWR2943 and 4 channels for AWR2944), with PCB antenna interface

Every transmission phase shifter

Ultra Accurate Linear Frequency Modulation Pulse Engine Based on Fractional N PLL

TX power

13.5dBm

RX noise coefficient

12dBm

Phase noise at 1MHz

-96dBc/Hz (76 to 77 GHz)

-95dBc/Hz (76 to 81GHz)

Built in calibration and self check

Built in firmware (ROM)

A system for self calibration of processes and temperatures

Processing Components

Arm Cortex-R5F kernel (supports lock step operation) @ 300MHz

TI Digital Signal Processor C66x @ 360MHz

TI radar hardware accelerator (HWA2.1) for FFT, logarithmic amplitude, memory compression, and other operations

Multiple EDMA instances for data mobility

Host interface

2x CAN-FD

10/100Mbps RGMII/RMII/MII Ethernet

Support for serial flash memory interface (loading user applications from QSPI flash memory)

Other interfaces provided for user applications

Up to 9 ADC channels

2 SPIs

4 UARTs

I 2C

GPIO

3 EPWMs

Four channel Aurora LVDS interface for raw ADC data and debugging instruments

CSI2 Rx interface can playback captured data

On chip RAM

3.5MB to 4MB (3.5MB for AWR2943 and 4MB for AWR2944)

Memory space is allocated between DSP, MCU, and shared L3

Device safety (on some device models)

Programmable Embedded Hardware Security Module (HSM)

Support for authenticated and encrypted secure boot

Customer programmable root key, symmetric key (256 bits), asymmetric key with key revocation function (up to RSA-4K or ECC-512)

Encryption hardware accelerator: PKA with ECC, AES (up to 256 bits), SHA (up to 512 bits), TRNG/DRGB

Targeting functional safety compliance

Developed specifically for functional safety applications

Relevant documents will be provided to assist in the design of functional safety systems that comply with ISO 26262 standards

Targeting hardware integrity up to ASIL B level

Complies with AEC-Q100 standards

Advanced features

Embedded self monitoring without the need for external processors

Embedded interference detection function

Power management

Built in LDO network to enhance PSRR

LVCMOS IO supports dual voltages of 3.3V and 1.8V

Clock source

40MHz crystal with internal oscillator

Supports external oscillators with a frequency of 40MHz

Support external drive, clock with a frequency of 40MHz (square wave/sine wave)

Optimized power management solution

Recommended LP87745-Q1 Power Management IC (PMIC)

A matching PMIC designed specifically to meet device power requirements

Flexible mapping and factory programming configurations, supporting multiple different use cases

Lower cost hardware design

0.65mm spacing, 12mm ×  12mm flip chip BGA packaging for easy assembly and low-cost PCB design

Small solution size

Supporting the temperature range of car operation

Working junction temperature range: -40 ° C to 140 ° C