XQ5VFX130T-1EF1738I

XQ5VFX130T-1EF1738I

XQV100-4CB228M

XQV300-4CB228M

XQ17V16C44M

XQR17V16CC44V 

XQ5VFX130T-1EF1738I  

XQ18V04VQ44N 

XQF32PVOG48M 

XQ2V1000-4CG717M 

XQR2V3000-4CG717V 

XQ4VLX25-10SF363M 

XC7K325T-2FBG676I

XC7K325T-L2FFG676I

XC7K410T-2FBG676C

XC7K410T-2FFG900I

XC7K410T-2FFG900I

XQ5VFX130T-1EF1738I

XC7K420T-1FFG1156I

XC7VX415T-1FFG1157C

XC7Z045-1FFG900C

XC7Z100-1FFG1156I

XCR3256XL-12TQG144I

EK-K7-KC705-G

XC6VSX315T-1FFG1156I 

EK-Z7-ZC706-G

XC6VLX240T-1FFG1156I

XC7K410T-2FFG676I

XC4VSX55-10FFG1148I

XC2C32A-6QFG32I

XC5VFX100T-1FF1136I

XC5VFX30T-2FFG665C

XC6SLX150-3CSG484I

XC6SLX150T-2CSG484I

XC6SLX75-2CSG484I

XC7A100T-2CSG324I

XC7A200T-2SBG484I

XC7K160T-2FBG676C

XC7A75T-2FGG676I

EK-K7-KC705-G

5962-8754903VCA  SN54AC00-SP ACTIVE

 Quadruple 2-Input Positive-NAND Gates

1256290132@QQ.COM

SN54AC00-SP Description

The SN54AC00 device contains four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic.

SN54AC00-SP  Features

5962R87549:

Radiation Hardness Assurance (RHA) up to TID 
TID 100 krad (Si)

SEL/SEU Immune to 86 MeV

5962-87549:

Total Ionizing Dose 50 krad (Si)

2-V to 6-V VCC Operation

Inputs Accept Voltages to 6 V

Max tpd of 7 ns at 5 V

CD4011B-MIL CMOS Quad 2-Input NAND Gate

CD4011B-MIL

Description

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

Features

Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V

Buffered inputs and outputs

Standardized symmetrical output characteristics

Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C

100% tested for quiescent current at 20 V

5-V, 10-V, and 15-V parametric ratings

Noise margin (over full package temperature range:
    1 V at VDD = 5 V
    2 V at VDD = 10 V
    2.5 at VDD = 15 V

Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

Quad 2 Input—CD4011B
Dual 4 Input—CD4012B
Triple 3 Input—CD4023B

JM38510/05051BCA

5962-8773802GA

AD536AKDZ

AD574AKD

AD586TQ/883B

AD590MF

AD590MF/883B

AD843AQ

OP90GSZ

AD7841BSZ  

AD524BDZ  

AD582KD     

AD660SQ     

AD811SQ/883B

AD8522ARZ