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Help CenterAD9467BCPZ-250 Analog-to-Digital Converter for Broadband Wireless Communications Instrumentation
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Product Highlights
IF optimization capability used to improve SFDR.
Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.
Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.
Packaged in a Pb-free, 72-lead LFCSP package.
Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.
Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS.
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