Module Spare Parts 216GD61a HESG324436R3-A HESG324428

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216GD61a HESG324436R3-A HESG324428


States 4 and 5- Anal nýput Each analog input model is triplicated with 3-2-0 capability. Each module consists of three triplicated legs. State 4 is the failure of one of the analog input microprocessor modules. State 5 is the failure of one of the analog input circuits to an input module. The transitions from the initial state to the intermediate states representing an initial failure of one of three input micro processors or input circuits are given by: kl,4 = 3 na sipa kl,5 = 3 naniea X ica The transitions from the intermediate state to the initial state representing the repair of the initial failure are given by: k4,1 = Lipa k5,1 = Aic The transitions from the intermediate state to a spurious trip representing a failure in one of the two remaining input channels or main processors are given by: k4,2 = 2 (X•mp + XSipa + nica X•Sica) k 5,12 - 2 (XLsmp + Xsipa + xsim) Where: na = Number of analog input modules nica = Number of input circuits for each analog input module IS p = Safe failure rate for analog input microprocessor ,XS = Safe failure rate for analog input circuits ALipa = Effective repair rate of analog input microprocessor Aia = Effective repair rate of analog input circuit WIMPR MPR Associates, Inc. 320 King Street Alexandria, VA 22314 Calculation No. 426-001-CBS-01 States 6 and 7- Each digital output module has a triplicated output processor with a quad voter output circuit. State 6 is the failure of one of the inputs into the digital output microprocessor modules. State 7 is the failure of one of the digital output circuits. The transitions from the initial state to the intermediate states ate given by: kj,6 kl,7 3 md X•.pd 4 md nocd 1.sOd The transitions from the intermediate state to the initial state representing the repair of the initial failure are given by: k 6 ,1 k7, 1 /.Lood The transitions from the intermediate state to a spurious trip representing a failure in one of the two remaining input channels or main processors are given by: k6,12 = 2 (,Xsmp + X•Sp) + (5 / 3) noX ;sow k7, 12 = (5 / 4) (XSmp + XSopd) + '.So•d Where: md nocd XS ocd /-Lopd //Lood Number of digital output modules Number of output circuits for each digital output module Safe failure rate for digital output microprocessor Safe failure rate for digital output circuits Effective repair rate of digital output microprocessor Effective repair rate of digital output circuit

States 4 and 5- Anal nýput Each analog input model is triplicated with 3-2-0 capability. Each module consists of three triplicated legs. State 4 is the failure of one of the analog input microprocessor modules. State 5 is the failure of one of the analog input circuits to an input module. The transitions from the initial state to the intermediate states representing an initial failure of one of three input micro processors or input circuits are given by: kl,4 = 3 na sipa kl,5 = 3 naniea X ica The transitions from the intermediate state to the initial state representing the repair of the initial failure are given by: k4,1 = Lipa k5,1 = Aic The transitions from the intermediate state to a spurious trip representing a failure in one of the two remaining input channels or main processors are given by: k4,2 = 2 (X•mp + XSipa + nica X•Sica) k 5,12 - 2 (XLsmp + Xsipa + xsim) Where: na = Number of analog input modules nica = Number of input circuits for each analog input module IS p = Safe failure rate for analog input microprocessor ,XS = Safe failure rate for analog input circuits ALipa = Effective repair rate of analog input microprocessor Aia = Effective repair rate of analog input circuit WIMPR MPR Associates, Inc. 320 King Street Alexandria, VA 22314 Calculation No. 426-001-CBS-01 States 6 and 7- Each digital output module has a triplicated output processor with a quad voter output circuit. State 6 is the failure of one of the inputs into the digital output microprocessor modules. State 7 is the failure of one of the digital output circuits. The transitions from the initial state to the intermediate states ate given by: kj,6 kl,7 3 md X•.pd 4 md nocd 1.sOd The transitions from the intermediate state to the initial state representing the repair of the initial failure are given by: k 6 ,1 k7, 1 /.Lood The transitions from the intermediate state to a spurious trip representing a failure in one of the two remaining input channels or main processors are given by: k6,12 = 2 (,Xsmp + X•Sp) + (5 / 3) noX ;sow k7, 12 = (5 / 4) (XSmp + XSopd) + '.So•d Where: md nocd XS ocd /-Lopd //Lood Number of digital output modules Number of output circuits for each digital output module Safe failure rate for digital output microprocessor Safe failure rate for digital output circuits Effective repair rate of digital output microprocessor Effective repair rate of digital output circuit