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Sell DDR/DDR2/SDR RAM Module
Negotiable
MOQ: 500 Sets (Price negotiable depending on order volume and customization)
Key Specifications
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Brand Name:
Place of Origin:
China
Model Number:
Payment & Shipping
Payment Methods:
Port of Shipment:
China
Delivery Detail:
7 days
Related Products
Place of Origin
China
Model No.:
Product Origin:China
Brand Name:
Price Terms:EXW
Payment Terms:T/T in advance
Certification:CE/FCC
Description:Features: 1) Lead-free 2) 1.8V power supply 3) Data rate: 667Mbps 4) 1.8V (SSTL-18 compatible) I/O 5) Double-data-rate architecture: two data transfers' per clock cycle 6) Bi-directional, differential data strobe (DQS and /DQS) is transmitted/ received with data, to be used in capturing data at the receiver 7) DQS is edge aligned with data for reads, center aligned with data for writes 8) Differential clock inputs (CK and /CK) 9) DLL aligns DQ and DQS transitions with CK transitions 10) Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 11) Four internal banks for concurrent operation (component) 12) Data mask (DM) for write data 13) Burst lengths: 4, 8 14) CAS latency (CL): 3, 4, 5 15) Auto precharge operation for each burst access 16) Auto refresh and self refresh modes 17) 7.8us average periodic refresh interval 18) Posted CAS by programmable additive latency for better command and data bus efficiency 19) Off-chip-driver impedance adjustment and on-die-termination for better signal quality 20) DQS can be disabled for single-ended data strobe operation Packing: Retail sealed packing, bulk packing
Product Origin:China
Brand Name:
Price Terms:EXW
Payment Terms:T/T in advance
Certification:CE/FCC
Description:Features: 1) Lead-free 2) 1.8V power supply 3) Data rate: 667Mbps 4) 1.8V (SSTL-18 compatible) I/O 5) Double-data-rate architecture: two data transfers' per clock cycle 6) Bi-directional, differential data strobe (DQS and /DQS) is transmitted/ received with data, to be used in capturing data at the receiver 7) DQS is edge aligned with data for reads, center aligned with data for writes 8) Differential clock inputs (CK and /CK) 9) DLL aligns DQ and DQS transitions with CK transitions 10) Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 11) Four internal banks for concurrent operation (component) 12) Data mask (DM) for write data 13) Burst lengths: 4, 8 14) CAS latency (CL): 3, 4, 5 15) Auto precharge operation for each burst access 16) Auto refresh and self refresh modes 17) 7.8us average periodic refresh interval 18) Posted CAS by programmable additive latency for better command and data bus efficiency 19) Off-chip-driver impedance adjustment and on-die-termination for better signal quality 20) DQS can be disabled for single-ended data strobe operation Packing: Retail sealed packing, bulk packing
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Business Type
Trading Company
Total Employees
101 - 200 People
Main Markets
North America, South America, Eastern Europe
Location
Dezhou, Shandong, China
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