AM29F010-90PC 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

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1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Description:

The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memoryorganized as 131,072 bytes. The Am29F010 is offeredin 32-pin PLCC, TSOP, and PDIP packages. The byte-wide data appears on DQ0-DQ7. The device is de-signed to be programmed in-system with the standardsystem 5.0 Volt VCC supply. A 12.0 volt VPP is not re-quired for program or erase operations. The device can

also be programmed or erased in standard EPROMprogrammers.The standard device offers access times of 45, 55, 70,90, and 120 ns, allowing high-speed microprocessorsto operate without wait states. To eliminate bus con-tention the device has separate chip enable (CE#),write enable (WE#) and output enable (OE) controls.The device requires only a single 5.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with theJEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-dard microprocessor write timings. Register contentsserve as input to an internal state machine that controlsthe erase and programming circuitry. Write cycles alsointernally latch addresses and data needed for the pro-gramming and erase operations. Reading data out ofthe device is similar to reading from other Flash orEPROM devices.Device programming occurs by executing the programcommand sequence. This invokes the EmbeddedProgram algorithm—an internal algorithm that auto-matically times the program pulse widths and verifiesproper cell margin.Device erasure occurs by executing the erase com-mand sequence. This invokes the Embedded Erasealgorithm—an internal algorithm that automatically pre-programs the array (if it is not already programmed) be-fore executing the erase operation. During erase, thedevice automatically times the erase pulse widths andverifies proper cell margin.The host system can detect whether a program orerase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a programor erase cycle has been completed, the device is readyto read array data or accept another command.

The sector erase architecture allows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is erasedwhen shipped from the factory.The hardware data protection measures include alow VCC detector automatically inhibits write operationsduring power transitions. The hardware sector pro-tection feature disables both program and erase oper-ations in any combination of the sectors of memory,and is implemented using standard EPROM program-mers.The system can place the device into the standby mode.Power consumption is greatly reduced in this mode.AMD’s Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability, and costeffectiveness. The device electrically erases all bitswithin a sector simultaneously via Fowler-Nordheimtunneling. The bytes are programmed one byte at atime using the EPROM programming mechanism ofhot electron injection.

Applications:

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

n Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

Specifications: