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Sell Memory Modules
Negotiable
MOQ: 500 Sets (Price negotiable depending on order volume and customization)
Key Specifications
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Business Type:
Trading Company
Year Established:
2001
Total Employees:
101 - 200 People
Payment & Shipping
Payment Methods:
Port of Shipment:
China
Delivery Detail:
7 days
Related Products
Model No.:DDRII 533, DDRII 667
Product Origin:China
Brand Name:Buyer's label
Price Terms:FOB Shenzhen
Payment Terms:
Certification:
Description:Specifications: 1) DDR2 533MHz, DDR2 667MHz 2) 240-pin socket type dual in line memory module (DIMM) 3) Lead-free 4) 1.8V power supply 5) Data rate: 533MBps, 667MBps 6) 1.8V (SSTL_18 compatible) I/O 7) Double-data-rate architecture: two data transfers per clock cycle 8) Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver 9) DQS is edge aligned with data for reads: center aligned with data for writes 10) Differential clock inputs (CK and /CK) 11) DLL aligns DQ and DQS transitions with CK transitions 12) Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 13) Four internal banks for concurrent operation (component) 14) Data mask (DM) for write data 15) Burst lengths: 4, 8 16) CAS Latency (CL): 3, 4, 5 17) Auto pre-charge operation for each burst access 18) Auto refresh and self refresh modes 19) 7.8us average periodic refresh interval 20) Posted CAS by programmable additive latency for better command and data bus efficiency 21) Off-chip-driver impedance adjustment and on-die-termination for better signal quality 22) DQS can be disabled for single-ended data strobe operation
Product Origin:China
Brand Name:Buyer's label
Price Terms:FOB Shenzhen
Payment Terms:
Certification:
Description:Specifications: 1) DDR2 533MHz, DDR2 667MHz 2) 240-pin socket type dual in line memory module (DIMM) 3) Lead-free 4) 1.8V power supply 5) Data rate: 533MBps, 667MBps 6) 1.8V (SSTL_18 compatible) I/O 7) Double-data-rate architecture: two data transfers per clock cycle 8) Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver 9) DQS is edge aligned with data for reads: center aligned with data for writes 10) Differential clock inputs (CK and /CK) 11) DLL aligns DQ and DQS transitions with CK transitions 12) Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 13) Four internal banks for concurrent operation (component) 14) Data mask (DM) for write data 15) Burst lengths: 4, 8 16) CAS Latency (CL): 3, 4, 5 17) Auto pre-charge operation for each burst access 18) Auto refresh and self refresh modes 19) 7.8us average periodic refresh interval 20) Posted CAS by programmable additive latency for better command and data bus efficiency 21) Off-chip-driver impedance adjustment and on-die-termination for better signal quality 22) DQS can be disabled for single-ended data strobe operation
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Business Type
Trading Company
Year Established
2001
Total Employees
101 - 200 People
Main Markets
North America, South America, Eastern Europe
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