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Overview
Highest Performance FPGA and SoC at 20 nm
Arria 10® FPGAs and SoCs deliver the highest performance at 20 nm offering a one speed-grade performance advantage over competing devices. Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPs).
- One speed grade faster than competing FPGAs and SoCs
- The industry’s only midrange 28.3 Gbps support
- Highest performance 2,666 Mbps DDR4 SDRAM memory interface
- IEEE 754-compliant hard floating-point with 1,500 GFLOPS of DSP performance
- 96 transceiver lanes deliver 3.6 Tbps of serial bandwidth
Up to 40% Lower Power than Previous-Generation FPGAs and SoCs
- Programmable power technology–Reduce device power in lower performance circuits while also delivering highest performance where needed
- Smart voltage ID–Operate devices to run optimum lower voltage without impacting performance
- VCC power manager–Operate devices at multiple voltage levels for either higher performance or lower power
- Low static power grades–Select devices with lower maximum static power
Industry’s Only 20 nm ARM-Based SoC
- Multiple SoC choices with dual-core ARM® Cortex®-A9 MPCore™ hard processor system (HPS)
- 1.5 GHz CPU operation per core
- Move existing Arria V SoC designs in 28 nm to Arria 10 SoC with no changes to processor code
- Learn more about the Arria 10 SoC
Save Board Space with Integration
- 2X more density versus the previous generation midrange with over 1 million logic elements (LEs)
- Hard intellectual property (IP) cores: DDR4 memory controllers and PCI Express® (PCIe®) 3.0 specification (Gen3)
- Enpirion® PowerSoCs offer customers the smallest footprint, highest performance, lower system power, higher reliability and efficiency, and faster time-to-market to power Arria 10 FPGAs and SoCs
Arria® 10 Device Family Variations
| Variant | Description |
|---|---|
| Arria 10 GT | FPGAs enabled with up to 96 full-duplex transceivers with data rates up to 28.3 Gbps chip-to-chip, 17.4 Gbps backplane and up to 1,150K equivalent LEs |
| Arria 10 GX | FPGAs enabled with up to 96 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 1,150K equivalent LEs |
| Arria 10 SX | SoCs enabled with a dual-core ARM Cortex-A9 HPS, up to 48 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip, 16.0 Gbps backplane, and up to 660K equivalent LEs |
Arria 10 Architecture
High Bandwidth, Low Latency Transceivers
Arria 10® FPGA and SoC serial transceivers offer high bandwidth, low latency, and the lowest power to help you build high-speed communication systems. Whether getting data across a board, distributing data to server blades across a backplane, moving data to the next chassis in a data center, or transporting data across the world through a sophisticated optical transport network, the Arria 10 FPGA and SoC transceivers provide a wide range of capabilities to support an extensive set of protocols and deliver reliable bandwidth with low cost.
Arria 10 SoCs: When Architecture Matters
SoCs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. The Arria 10 SoCs, based on TSMC’s 20 nm process technology, combine a dual-core ARM® Cortex™-A9 MPCore™ hard processor system (HPS) with industry-leading programmable logic technology that includes hardened floating-point digital signal processing (DSP) blocks.
Hardened Floating-Point DSP Blocks
In Arria 10 devices, Altera has enhanced the variable-precision DSP block by including hardened floating-point operators. The Arria® 10 FPGA and SoC variable-precision DSP block introduces a new floating-point mode that delivers breakthrough floating-point performance of up to 1.5 TeraFLOPs.
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