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Dual cores in stock tray packing 1.73GHz 1M 533MHz Intel Celeron Mobile T1400 SLAQL CPU

Name: Dual cores in stock tray packing 1.73GHz 1M 533MHz Intel Celeron Mobile T1400 SLAQL CPU
Brand: Intel
Price: Negotiable

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10 Pieces(Min.Order)

Product Details

Dual cores in stock tray packing 1.73GHz 1M 533MHz Intel Celeron Mobile T1400 SLAQL CPU

General information

Type	CPU / Microprocessor
Family	Intel Mobile Celeron Dual-Core
Processor number ?	T1400
Part number	LF80537NE030512
Frequency (GHz) ?	1.733
Bus speed (MHz) ?	533
Clock multiplier ?	13
Package type	478-pin micro-FCPGA
Socket type	Socket P

Architecture / Microarchitecture / Other

Core stepping	M0
Processor core	Merom-2M
Manufacturing technology (micron)	0.065
Number of cores	2
L2 cache size (KB) ?	512
Features	EM64T technology ? Execute disable bit ?

There are no notes on sSpec SLAQL

In addition to the SLAQL S-Spec, this processor was also manufactured with one pre-production S-Spec number:

Stepping	S-Spec	LF80537NE030512
M0	Q9AB	+
M0	SLAQL	+

NOTE: Engineering and qualifications samples are marked with this color

View / search public CPUID submissions

Intel Celeron Dual-Core Mobile T1400 SLAQL

Part number:	LF80537NE030512
Frequency:	1728 MHz

Comment:
Submitted by:	CPU-World

General information
Vendor:	GenuineIntel
Processor name (BIOS):	Genuine Intel(R) CPU T1400 @ 1.73GHz
Cores:	2
Logical processors:	2
Processor type:	Original OEM Processor
CPUID signature:	6FD
Family:	6 (06h)
Model:	15 (0Fh)
Stepping:	13 (0Dh)
TLB/Cache details:	64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache:	L1 data	L1 instruction	L2
Size:	32 KB	32 KB	512 KB
Associativity:	8-way set associative	8-way set associative	2-way set associative
Line size:	64 bytes	64 bytes	64 bytes

Instruction set extensions		Additional instructions

MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
SSSE3		FXSAVE/FXRSTORE
		MONITOR/MWAIT
		SYSENTER/SYSEXIT

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
		CPL qualified debug store
		Debug store
		Debugging extensions
		Digital Thermal Sensor capability
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Self-snoop
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control

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