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Help Center1066 1333 1600 RAM DDR3 Memory 1GB 2GB 4GB
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DDR3 1333 1600 2GB 4GB 8GB
Item Name |
DDR3 4GB 1333MHZ Memory Moudle for Desktop |
| Application | desktop |
| Speed | 1333MHZ |
| Compatible | Full compatible/working with all motherboard |
| Warranty | 2 years |
| Brand | OEM&ODM service |
| Original Chip | Kingston,Hynix.Micron. Samgsung. Nanya. |
| Module Type | PC3-12800 CL9 Non-ECC ram |
| Function | Non-ECC Memory |
| No. of Pins | 240Pins Long-DIMM ram |
| RMA | RMA rate less 1%,Goods tested before delivery |
| MOQ | 50 pieces for each model. Sample Orders also highly welcome. |
| Price terms | China factory price. |
| Payment | T/T,Western Union & MoneyGram,Paypal |
| Delivery date | 1-3 working days |
| Packing | Antistatic package(50pieces/ tray box) |
| Shipment | By DHL,EMS & Air Cargo according your requirments. |
Other Key information:
1) DDR 400/333 & DDRII 533/667/800 & DDR3/1066/1333/1600 MHz.
2) 168/184/240-pin socket type dual in line memory module (DIMM) .
3) 2.6V power supply
4) Data rate: 400/333/533/667/800M1066/1333MHZ/1600mhz (max).
5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8Vpower supply for DDR II products
6) Double-data-rate architecture, two data transfers per clock cycle.
7) Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be
used in capturing data at the receiver
8) Data inputs and outputs are synchronzed with DQS.
9) DQS is edge aligned with data for read, center aligned with data for write.
10) Differential clock inputs (CK and CK).
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge: Data and data mask referenced to both edges of DQS.
13) Four internal banks for concurrent operation (component).
14) Data mask(DM) for write data.
15) Auto precharge option for each burst access
16) Programmable burst length: 2, 4, 8
17) Programmable/CAS latency (CL): 3
18) Programmable output driver strength: Normal/weak
19) Refresh cycles: (8192 refresh cycles/64ms) .
20) 7.8US maximum average periodic refresh interval.
21) Posted CAS by programmable additive latency for better command and data bus efficiency
22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality .
23) DQS can be disabled for single-ended data strobe operation
24) 2 variations of refresh
25) Auto refresh
26) Self refresh.
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